The invention relates to universal asynchronous receiver/transmitter (UART) interfaces that are in widespread use for communicating between a host device, such as a computer, and an external subsystem, such as a mobile telephone, plug-in card or another computer.
In order to interface the parallel data bus of a computer to an external subsystem using a serial communication channel, an interface is required to convert parallel bytes into serial bits and serial bits into parallel bytes, depending on the direction of the communication. An industry standard interfacing device for performing this function is the UART. In addition to converting data between parallel byte and serial bit format, UARTs are also responsible for managing other aspects of asynchronous data transfer. For example, UARTs set the timing of bit transfer, perform parity checking (if used), add the start and stop control signals to a transmitted data stream and also strip them from a received data stream. One common family of UART devices is those conformant to the standards set by the National Semiconductor 16550 chip.
Corresponding synchronous devices, referred to as USARTs (Universal Synchronous Receiver/Transmitters) also exist.
FIG. 1 illustrates a standard 16550 UART connected between a host 10 and subsystem 50 to provide an asynchronous communications capability. The 16550-type UART 20 is shown interfaced on one side to the host 10 via a data bus 12 and on the other side to the subsystem 50 via a bidirectional serial communication channel 52 comprising a transmission line TX and a receiver line RX. The UART 20 includes a register set 22 made up of a number of eight-bit registers. Register THR is a transmitter holding register, register RBR is a receiver buffer register, register IER is an interrupt enable register, register IIR/FCR is an interrupt identification/first-in-first-out (FIFO) control register, register LCR is a line control register, register MCR is a modem control register, register LSR is a line status register, register MSR is a modem status register, register SCR is a scratch register, register DLL is a least significant bits division latch register and register DLH is a most-significant bits division latch register.
The UART 20 includes a 16-byte transmit FIFO buffer 24 paired with a parallel-to-serial (P-S) converter 25, and a 16-byte receive FIFO buffer 26 paired with a serial-to-parallel (S-P) converter 27. The UART 20 also includes interrupt request (IRQ) logic 13 and a baud-rate generator (BRG) 8. The main connections to and from the UART 20 are indicated in the figure and include a transmission line TX, a receiver line RX, a modem control output (MCO) 6, a modem status input (MSI) 4, an oscillator crystal input (OSC) 2, an interrupt request output (IRQ) 14 and a data bus 12 for communicating with the host. Industry standard addresses are associated with each of the registers such that the operating system of the host can access (i.e. read from or write to) the registers as required via the data bus 12.
To send a byte of data from the host to the subsystem along the serial transmission line TX, the byte of data is first written to the THR register via the data bus 12. The UART transfers the byte of data into the 16-byte transmit FIFO buffer 24 for temporary storage. The purpose of the transmit FIFO buffer 24 is to allow the host computer to pass several bytes of data for transmission to the UART at a rate which is faster than the UART can process and send the data along the output serial communication channel. The byte of data (or the oldest byte of data resident in the transmit FIFO buffer 24 if it is not otherwise empty) is then passed to the parallel-to-serial converter 25. The parallel-to-serial converter 25 functions to generate a start signal, serialize the byte into eight sequential bits and generate a stop signal and supply these data bits at an agreed bit rate to the transmission line TX.
To receive a byte of data from the subsystem along the serial receiver line RX, the UART is first alerted to incoming data by a start signal supplied by the subsystem. This is detected by the serial-to-parallel converter 27 which monitors the receiver line RX awaiting the arrival of start signals indicating that the subsystem is about to send data. When a start signal is detected, the serial-to-parallel converter 27 samples the receiver line RX at a previously agreed bit-rate to determine eight sequential bits of data sent by the subsystem. A stop signal from the subsystem confirms the end of data transfer. The data bits are parallelized to form a byte which is then written to the 16-byte receive FIFO buffer 26. The purpose of the receive FIFO buffer 26 is to allow several bytes of data to be received by the host without an interrupt being generated for each byte. Several received bytes can be deposited into the receive FIFO buffer 26 and transferred to the host on a single interrupt. On interrupt, each received byte is written from the receive FIFO buffer 26 into the RBR register in turn. The host retrieves the data byte via the data bus 12.
The functions of the remaining registers and the other components shown in the figure are not discussed further for brevity. However, these features are standard and well known.
In summary, UART interface devices act as communications elements, passing data between parties to a data transfer as serial bit-streams. Due to a wide adoption of the 16550-type UART device (virtually every desktop Personal Computer (PC) of the “IBM Compatible” type contains at least one such UART), most computer operating systems include device drivers which offer generic support for this type of UART. Subsystems which adopt the 16550-type UART register set and conform to the “industry standard” 16550-type UART functionality can expect support on a wide range of computer platforms, including Personal Digital Assistant (PDA) platforms and miniature hand-held PCs.
The standard 16550-type UART can support serial data transfer rates of up to 115,200 bits-per-second (bps). The 16-byte transmit and receive FIFO buffers allow the use of such bit rates with continuous flows of data by providing a temporary store for data before being recovered by the host computer, or serialized by the UART's parallel-to-serial converter, as discussed above. To improve the performance capabilities of 16550-type UARTs it has been proposed to use larger transmit and receive FIFO buffers, for example up to 128-byte FIFO buffers. These “FIFO-enhanced” 16550-type UARTs devices offer the advantage that more data can be stored on a temporary basis which in-turn allows a greater fluctuation in device driver response time which can be accommodated without data corruption. In this context, the driver response time, or latency, is defined as the period between “bursts” of activity. These bursts are normally triggered by a hardware interrupt from the UART to request service from the driver in order to keep the transmit FIFO buffer filled before it under-runs, or to empty the receive FIFO buffer before it over-runs. The latter is the most serious condition as it will result in data loss rather than degraded performance.
Increasing the size of the transmit and receive FIFO buffers in a 16550-type UART improves performance, but the underlying transfer mechanism remains that of an asynchronous serial bit-stream. This transfer mechanism inherently imposes speed limitations, because of the need to serialize the data and the inefficient use of available bandwidth. An additional problem with increasing the size of the internal transmit and receive FIFO buffers is that they use a large amount of silicon area. They also require modification of existing device drivers since these are conventionally written for 16-bytes transmit and receive FIFO buffers.
The basic 16550-type UART therefore offers a simple, convenient and well supported method of data transfer between a host computer and its subsystems, but one which imposes limitations on the transfer of large blocks of data or for continuous data transfer.
Some specific examples of improvements on the basic 16550-type UART are now briefly summarized.
U.S. Pat. No. 6,434,161 [ref. 1] describes an “emulated UART” in which the regular serial communication channel is effectively replaced with a parallel communication channel by allowing bytes to be transferred between a host computer and a subsystem using a Direct Memory Access (DMA) method. The emulated UART can operate faster because there is no need to serialize or de-serialize the data. The data transfer is done in parallel without any temporary buffering of the bytes.
U.S. Pat. No. 6,381,661 [ref. 2] describes a UART connected to a additional device, termed a UDIF, that takes data from the UART serial communication channel and re-buffers it into a parallel format so that it can be more efficiently accessed by a subsystem.
U.S. Pat. No. 6,260,086 [ref. 3] describes an improved method for loading multiple data words into, or from, the internal transmit and receive FIFO buffers in a UART. The method employs more efficient microprocessor instructions which have explicit addresses aliased back to a single address, i.e. the data address of the transmit or receive FIFO buffers.
U.S. Pat. No. 6,201,817 [ref. 4] describes a command processor for decoding data streams flowing serially in and out of a UART. The decoder reduces the processing overhead of a subsystem processor when determining whether special characters or sequences of characters are present in the data.
U.S. Pat. No. 5,557,751 [ref. 5] describes a system in which serial data flow is directed to the normal internal UART registers, and then buffered by additional FIFO buffers. The additional FIFO buffers are larger than the internal transmit and receive FIFO buffers, and can be accessed by the subsystem in a manner appropriate to its local bus.
The prior art approaches can be classified into two groups.
The first approach [e.g. refs. 3, 4, 5] provides improvements on how data is handled at the receiver or sender at either end of the serial channel. This approach can provide significant improvements, but data transfer rates are ultimately limited by the serial channel.
The second approach [e.g. refs. 1, 2] overcomes the speed limitations of the serial channel by replacing it with a parallel channel. Higher data transfer rates are thus achieved. However, compatibility with the 16550-type UART standard is lost. Loss of this compatibility creates a great deal of additional development work when implementing a UART interface for a new subsystem. For example, extensive rewriting of standard device drivers is often required.